Circuit Placement : 2000 - Caldwell , Kahng ,
نویسندگان
چکیده
This problem is concerned with efficiently determining constrained positions of objects while minimizing a measure of interconnect between the objects, as in physical layout of integrated circuits, commonly done in 2-dimensions. While most formulations are NP-hard, modern circuits are so large that practical algorithms for placement must have near-linear runtime and memory requirements, but not necessarily produce optimal solutions. While early software for circuit placement was based on Simulated Annealing, research in algorithms identified more scalable techniques which are now being adopted in the Electronic Design Automation industry. One models a circuit by a hypergraphGh(Vh, Eh) with (i) vertices Vh = {v1, . . . , vn} representing logic gates, standard cells, larger modules, or fixed I/O pads and (ii) hyperedges Eh = {e1, . . . , em} representing connections between modules. Every incident pair of a vertex and a hyperedge connect through a pin for a total of P pins in the hypergraph. Each vertex vi ∈ Vh has width wi, height hi and area Ai. Hyperedges may also be weighted. Given Gh, circuit placement seeks center positions (xi, yi) for vertices that optimize a hypergraph-based objective subject to constraints (see below). A placement is captured by x = (x1, · · · , xn) and y = (y1, · · · , yn).
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